In-person event

DAC

June 23-27, 2024 in San Francisco, US

The global event for chips to systems.
27 Expertise. paper & poster presentations.
3 Insightful. gladiator sessions.
10+ Network. experts on site.

Shaping the next generation of electronics

The Design Automation Conference (DAC) offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

 

This year ST will demonstrate its innovative solutions and methodologies in the field of not only designs but also how to build them. ST's experts will share their visions in the new era of design and verification flows, helping engineers design and create state-of-the-art solutions and reach the market on time while ensuring the highest quality. 

 

Atul Bhargava, ST Senior Group Manager and Senior Member of Technical Staff is also part of the DAC front-end technical program committee.  

We have several paper and poster presentations on the agenda showcasing our latest research on a variety of focus areas. You will also find us in the *Gladiator Arena with three presentations. Follow our agenda below!

Join ST speakers and discover their visions in the new era of design and verification flows

Presentation program - June 24

  

24 June | Paper presentation
11.10 AM

Pruning netlist: A smarter approach to efficient and reliable circuit characterization

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

24 June | Paper presentation
2.15 PM

Window feedback based multi-master arbiter IP for efficient hardware resource sharing

Speaker

Gianluca Rigano | IC Design and Verification engineer

24 June | Paper presentation
2.30 PM

An all-digital IP for fast correction of time-skew mismatch in time-interleaved analog to digital converters for communication receivers

Speaker

Aradhana Kumari, Technical leader

24 June | Paper presentation
2.45 PM

Automatic layout symmetry annotation via graph node embeddings

Speaker

Jerome Lescot | Senior Member of Technical Staff

Presentation program - June 25

  

25 June | Paper presentation
10.30 AM

Advancing power signoff for high speed sigma delta ADC

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

25 June | Paper presentation
10.45 AM

Selective resistance extraction for performance accuracy trade-off

Speaker

Ashish Kumar | Group Manager & Member of Technical Staff

25 June | Paper presentation
11.00 AM

Fast and deterministic memory yield estimation using machine learning augmented statistical simulations

Speaker

Ashish Kumar | Group Manager & Member of Technical Staff

25 June | Paper presentation
11.15 AM

Low-cost built in self test IP for next gen continuous time sigma delta ADCs

Speaker

Ankur Bal | Director Technology R&D group

25 June | Paper presentation
11.30 AM

An all-digital transient filter IP for serial links

Speaker

Aradhana Kumari | Technical leader

25 June | Paper presentation
2.00 PM

Enhancing quality and reducing verification effort for RTL implementations against high-level C/C++ models using formal equivalence

Speaker

David Vincenzoni | Formal Verification expert 

25 June | Paper presentation
2.30 PM

Beyond digital: innovation in symbolic simulator to empower IO analog circuit validation

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

Poster sessions- June 24-26

Join ST experts for insightful DAC poster sessions.

  

24 June | Engineering track poster session
5.00 PM

An integrated behavioral modeling method for mixed signal IPs

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

24 June | Engineering track poster session
5.00 PM

Achieving high local noise coverage in dynamic EMIR analysis using SigmaDVD

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster session
5.00 PM

Quality assurance of device rules by Cadence SKILL automation

Speaker

Kancou Traore | Design Foundation Automation team leader

24 June | Engineering track poster session
5.00 PM

Automated place & route-based solution for custom blocks

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster session
5.00 PM

Novel way of checking and analyzing peak to peak voltage variation challenges for high computational multiprocessors SOC

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster session
5.00 PM

Faster timing closure of multiple power domain-based designs with SMVA

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

25 June | Engineering track poster session
5.00 PM

Accelerating .lib characterization with AI

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

25 June | Engineering track poster session
5.00 PM

Resolving the seed promotion due to device layers derivation

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

25 June | Engineering track poster & Gladiator session
5.15 PM

Early SoC enablement using prelim generator

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

25 June | Engineering track poster & Gladiator session
5.15 PM

A novel flow to verify SoC integration with formal property verification

Speaker

David Vincenzoni | Formal Verification expert

25 June | Engineering track poster session
5.20 PM

Early detection of low power related issues using formal verification

Speaker

Andrea Michele Lopinto | Digital Verification Engineer 

25 June | Engineering track poster & Gladiator session
5.30 PM

Challenges and improvements in standard cell OpenAccess content for analog design

Speaker

Ashish Kumar | Group Manager & Member of Technical Staff

25 June | Engineering track poster session
5.30 PM

Autonomous power sequence validation solution for I/O using Solido design environment

Speaker

Atul Bhargava | Senior Group Manager (Technology & Design Platform)

25 June | Engineering track poster session
5.30 PM

Machine learning-based feasibility estimation of digital blocks for improved productivity in analog-on-top back-end design flows

Speaker

Gabriele Faraone | Digital Layout engineer

25 June | Engineering track poster session
5.40 PM

Enhancing and accelerating verification with ad hoc python scripting

Speaker

Davide Sanalitro | Product Digital Verification expert 

26 June | Work in progress poster session
5.00 PM

Advanced analog design optimization: comparison between reinforcement learning and heuristic algorithms

Speaker

Michel Chevalier

Register for DAC 2024

Join ST at DAC 2024 and discover our innovative solutions and methodologies in the field of designs!

On

23 - 27 Jun, 2024

In

San Francisco, US
Get your pass
Moscone West, Convention Center

San Francisco, US

Map of DAC 2024 Map of DAC 2024 Get your pass

Register for DAC 2024

Join ST at DAC 2024 and discover our innovative solutions and methodologies in the field of designs!

23 - 27 Jun, 2024

San Francisco, US

Map of DAC 2024 Get your pass