Arm® Cortex®-M3 in a nutshell
The 32-bit Arm® Cortex®-M3 core processor is designed for high-performance, real-time processing in cost-constrained applications and can handle complex tasks. Any Arm® Cortex®-M3 microcontroller offers high scalability combined with an optimal trade-off between performance and cost.
Key features of Arm® Cortex®-M3 core
- Armv7-M architecture
- Bus interface 3x AMBA AHB-lite interface (Harvard bus architecture) AMBA ATB interface for CoreSight debug components
- Thumb/Thumb-2 subset instruction support
- 3-stage pipeline
- Nested Vectored Interrupt Controller (NVIC)
- Optional 8 MPU regions with sub-regions and background region
- Integrated Bit-field Processing Instructions and Bus Level Bit Banding
- Non-maskable interrupt + 1 to 240 physical interrupts with 8 to 256 priority levels
- Wake-up interrupt controller
- Hardware single-cycle (32x32) multiply, Hardware Divide (2-12 cycles), Saturated Adjustment support
- Integrated WFI and WFE Instructions and Sleep On Exit capability. Sleep and Deep Sleep Signal, Optional Retention Mode with Arm Power Management Kit
- Optional JTAG and Serial Wire Debug ports. Up to 8 breakpoints and 4 watchpoints
- Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)
Arm Cortex-M3 block diagram State-of-the-art Arm® Cortex®-M3 MCU series
Small footprint
The small footprint of the core allows it to be used either as a single core in small devices or as an additional embedded companion core when specific hardware isolation or task partitioning is required. Thanks to the advancements in silicon manufacturing technologies, the lithography process moved from 180 to 90nm and lower, and the core silicon real-estate now reaches 0.03mm² in 90nm lithography.
In a similar way as Cortex®-M0 and Cortex®-M0+, the Cortex®-M3 core has a low impact on the trade-off to be made among the typical elements of an MCU architecture, based on I/Os, analog and non-volatile memories. The bus size (8, 16 or 32 bits) is therefore no longer relevant when partitioning MCU portfolios.
Cortex®-M3 microcontrollers are widely used and offer several benefits:
- They meet performance requirements in entry-level applications.
- They are also suitable for general-purpose applications.
- The architecture of the Arm® Cortex®-M3 processors offers high scalability and allows existing designs to be reused across different projects.
- And, thereby allows you to lower overall ownership costs and ease development steps.
Dynamic power consumption from 10 to 150µW/MHz
The dynamic power of the core ranges from 10 to 150µW/MHz depending on the technology used. However, the core itself is not representative of the overall power consumption of a device and is not the only factor to take into account. It is therefore important to carefully read product datasheets.
The Thumb instruction set is a subset of the Cortex-M family. It eases the scalability of the portfolio by re-using validated software bricks for any Cortex-M products.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) manages the CPU's access to the memory. It ensures that a task does not accidentally corrupt the memory or the resources used by other active tasks. The MPU is usually controlled by a Real-Time Operating System (RTOS).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.
Microcontrollers based on the Arm® Cortex®-M3
Get started developing on Arm® Cortex®-M3 core with our recommended starter kit
NUCLEO-L152RE
STM32 Nucleo-64 development board with STM32L152RE MCU, supports Arduino and ST morpho connectivity
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Arm® Cortex®-M3
Exceptional 32-bit performance with low power consumption
