Product overview
Description
Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected updatable automated and electrified cars. They have superior real-time and safe performance (with highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple source software onto the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation at almost no memory overhead thanks to SR6 unique built-in dual-image storage tailored to OTA reprogramming needs. They also provide high-speed security cryptographic services, for instance for network authentication.
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All features
- AEC-Q100
- SR6 integration MCUs:
- Have superior real-time and safe performance (with highest ASIL-D capability)
- Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance
- Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage)
- Offer high-speed security cryptographic services, for example for network authentication
- Cores
- 6 × 32-bit Cortex®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration):
- Configurable as either 6 cores (4 of them in lockstep configuration) or 5 cores (all of them in lockstep configuration)
- Arm® v8-R compliant
- Single precision floating-point unit (FPU)
- New privilege level for real-time virtualization
- 2 cores with Neon™ extensions (for example SIMD, dual precision FPU)
- 2 Cortex®‑M4 multipurpose accelerators, one in lockstep configuration
- 4 eDMA engines in lockstep configuration
- 6 × 32-bit Cortex®‑R52+ cores (4 of them with checker cores, and 2 in split-lock configuration):
- Memories
- Up to 20 MB on-chip nonvolatile memory (NVM):
- PCM (phase-change memory) as nonvolatile memory
- 19.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 19.5 MB
- 512 KB HSM-dedicated code NVM
- 640 KB data NVM (512 KB + 128 KB dedicated to HSM)
- Up to 8400 KB on-chip general-purpose SRAM
- Up to 20 MB on-chip nonvolatile memory (NVM):
- Security: 2nd generation hardware security module
- Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details)
- On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA)
- Symmetric and asymmetric cryptography processor
- High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services
- Safety: comprehensive new-generation ASIL-D safety concept
- New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities
- Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
- Peripheral, I/O, and communication interfaces
- 11 LINFlexD modules
- 2 dual-channel FlexRay controllers
- 10 queued serial peripheral interface (SPIQ) modules
- 4 microsecond channels (MSC) and 2 microsecond plus (MSC-Plus) channels
- 2 I²C interfaces
- 2 SENT modules (15 channels each)
- 2 PSI5 modules (1 channel each)
- Enhanced analog-to-digital converter system with:
- 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC).
- 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode
- 12 separate 16-bit sigma-delta analog converters with embedded DSP processor on each SD ADC
- Enhanced interconnection with GTM timer for autonomous ADC/GTM subsystem operation
- Advanced timed I/O capability:
- Generic timer module (GTM4154)
- High-resolution timer
- Communication interfaces:
- Two 10/100/1000 Mbit/s Ethernet controllers compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and EMC optimized SGMII
- 11 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD®)
- 2 CAN XL® interfaces
- External memory interfaces
- 2 octo-SPI IPs to support HyperBus™ memory (flash/RAM) devices
EDA Symbols, Footprints and 3D Models
STMicroelectronics - SR6P7C8
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3D models
Quality and Reliability
| Part Number | Marketing Status | Package | Grade | RoHS Compliance Grade | Material Declaration** |
|---|---|---|---|---|---|
| SR6P7C8A0xxCxxx | Proposal | FPBGA 516 25x25x0.8 | Industrial | - | |
SR6P7C8A0xxCxxx
Package:
FPBGA 516 25x25x0.8Material Declaration**:
(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.
Sample & Buy
| Part Number | Marketing Status | Budgetary Price (US$)*/Qty | Order from ST | Order from distributors | Package | Packing Type | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | CPU Clock Frequency (MHz) (max) | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| min | max | ||||||||||||||
| SR6P7C8A0xxCxxx | | | distributors No availability of distributors reported, please contact our sales office |
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SR6P7C8A0xxCxxx Proposal
(*) Suggested Resale Price (USD) per defined quantity for BUDGETARY USE ONLY. For quotes, prices in local currency, please contact your local ST Sales Office or our Distributors