Product overview
Description
STM32H7A3xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 280 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H7A3xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H7A3xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory up to 2 Mbytes, around 1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses, three AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.
All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers, a true random number generator (RNG). The devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces.
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All features
- Core
- 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Memories
- Up to 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of OTP
- ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
- 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode
- Flexible external memory controller with up to 32-bit data bus:
- SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode
- SDRAM/LPSDR SDRAM,
- 8/16-bit NAND Flash memory
- CRC calculation unit
- Security
- ROP, PC-ROP, active tamper, secure firmware upgrade support
- General-purpose input/outputs
- Up to 168 I/O ports with interrupt capability
- Fast I/Os capable of up to 133 MHz
- Up to 164 5 V-tolerant I/Os
- Up to 168 I/O ports with interrupt capability
- Low-power consumption
- Stop: down to 32 µA with full RAM retention
- Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)
- VBAT: 0.8 µA with RTC and LSE ON
- Clock management
- Internal oscillators: 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI
- External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
- 3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
- Reset and power management
- 2 separate power domains, which can be independently clock gated to maximize power efficiency:
- CPU domain (CD) for Arm® Cortex® core and its peripherals , which can be independently switched in Retention mode
- mart run domain (SRD) for reset and clock control, power management and some peripherals
- 1.62 to 3.6 V application supply and I/Os
- POR, PDR, PVD and BOR
- Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
- Dedicated MMC power supply
- High power efficiency SMPS step-down converter regulator to directly supply VCORE or an external circuitry
- Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
- Voltage scaling in Run and Stop mode
- Backup regulator (~0.9 V)
- Low-power modes: Sleep, Stop and Standby
- VBAT battery operating mode with charging capability
- CPU and domain power state monitoring pins
- 2 separate power domains, which can be independently clock gated to maximize power efficiency:
- Interconnect matrix
- 5 DMA controllers to unload the CPU
- 1× high-speed general-purpose master direct memory access controller (MDMA)
- 2× dual-port DMAs with FIFO and request router capabilities
- 1× basic DMA with request router capabilities
- 1x basic DMA dedicated to DFSDM
- Up to 35 communication peripherals
- 4× I2C FM+ interfaces (SMBus/PMBus)
- 5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART
- 6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz)
- 2x SAIs (serial audio interface)
- SPDIFRX interface
- SWPMI single-wire protocol master I/F
- MDIO Slave interface
- 2× SD/SDIO/MMC interfaces (up to 133 MHz)
- 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
- 1× USB OTG interfaces (1HS/FS)
- HDMI-CEC
- 8- to 14-bit camera interface up to 80 MHz
- 8-/16-bit parallel synchronous data input/output slave interface (PSSI)
- 11 analog peripherals
- 2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS)
- 1× analog and 1x digital temperature sensors
- 1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC
- 2× ultra-low-power comparators
- 2× operational amplifiers (8 MHz bandwidth)
- 2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2 channels/1 filter
- Graphics
- LCD-TFT controller up to XGA resolution
- Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
- Hardware JPEG Codec
- Chrom-GRC™ (GFXMMU)
- Up to 19 timers and 2 watchdogs
- 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 280 MHz)
- 2× 16-bit advanced motor control timers (up to 280 MHz)
- 10× 16-bit general-purpose timers (up to 280 MHz)
- 3× 16-bit low-power timers (up to 280 MHz)
- 2× watchdogs (independent and window)
- 1× SysTick timer
- RTC with sub-second accuracy and hardware calendar
- Debug mode
- SWD & JTAG interfaces
- 4 Kbytes Embedded Trace Buffer
- 1x 32-bit, NIST SP 800-90B compliant, true random generator
- 96-bit unique ID
- All packages are ECOPACK2 compliant
- Core
Circuit Diagram
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All resources
| Resource title | Version | Latest update |
|---|
System View Description (1)
| Resource title | Version | Latest update | ||
|---|---|---|---|---|
| ZIP | 1.9 | 23 Nov 2023 | 23 Nov 2023 |
IBIS models (1)
| Resource title | Version | Latest update | ||
|---|---|---|---|---|
| ZIP | 5.0 | 11 Mar 2024 | 11 Mar 2024 |
BSDL files (1)
| Resource title | Version | Latest update | ||
|---|---|---|---|---|
| ZIP | 5.0 | 14 Oct 2024 | 14 Oct 2024 |
Quality and Reliability
| Part Number | Marketing Status | Package | Grade | RoHS Compliance Grade | Material Declaration** |
|---|---|---|---|---|---|
| STM32H7A3LGH6Q | Active | TFBGA 225 13x13x1.2 P 0.8 mm | Industrial | Ecopack2 |
(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.
Sample & Buy
| Part Number | Marketing Status | Budgetary Price (US$)*/Qty | Order from ST | Order from distributors | Package | Packing Type | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | D/A Converters (typ) (12-bit) | Timers (typ) (16-bit) | Timers (typ) (32-bit) | Number of Channels (typ) | SMPS | Number of Channels (typ) | UART (typ) | I/Os (High Current) | Integrated op-amps | Comparator | SPI (typ) | USART (typ) | Number of Channels (typ) | I2S (typ) | Advanced Motor Control Timers | CAN (2.0) | CAN (FD) | Ethernet | ||
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| STM32H7A3LGH6Q | | | distributors No availability of distributors reported, please contact our sales office |
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STM32H7A3LGH6Q Active
(*) Suggested Resale Price (USD) per defined quantity for BUDGETARY USE ONLY. For quotes, prices in local currency, please contact your local ST Sales Office or our Distributors