Product overview
Description
The ST54L is a single-die solution integrating a contactless front-end (ST54L_CLF) and a secure element (ST54L_SE). It is designed for integration in mobile devices and NFC-compliant products.
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All features
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- Single die integrating an NFC controller (contactless front-end - CLF) and a secure element (SE)
- Small package WLCSP90, ECOPACK-compliant
- NFC controller
- Arm® Cortex®-M3 microcontroller
- 100% re-flashing capability for firmware update
- Enhanced active load modulation technology
- Enhanced Tx drive up to 2W
- Support of external DC/DC up to 5.5 V
- Highest output power with optimized power transfer
- Optimized for extremely small or metal frame antennas
- Optimized Low-power consumption modes
- Selectable ultralow power hibernate state
- Battery voltage monitoring
- Proprietary in-frame synchronization (IFS) in card emulation (CE) to ensure stability in battery low and switched off modes
- Improved XOR mode on all technologies
- OOFS with external reference clock in CE
- System clock
- Fractional-N PLL input range of 19.2 to 76.8 MHz
- Support of multiple external crystal oscillator (27.12 MHz and 54.24 MHz)
- 32.768 kHz, 16MHz and 32MHz support for EMC tests
- Automatic wakeup via communication interfaces, GPIO, RF field or tag detection and power supply detection
- RF communications
- Active and passive peer-to-peer
- ISO/IEC 18092 - NFCIP-1 initiator and target
- Reader/writer mode
- NFC Forum™ Type 1/2/3/4/5 tags
- FeliCa™
- ISO/IEC 15693
- MIFARE®1
- Card emulation mode
- ISO/IEC 14443 Type A & B
- FeliCa™
- Intelligent Card Switching
- MIFARE®
- Active and passive peer-to-peer
- Communication interfaces
- I3C interfaces:
- ST54L_CLF: 1 target up to 12.9 MHz, 1 controller - target up to 12.9 MHz, 1 controller up to 12.9 MHz
- ST54L_SE: 1 target up to 12.9 MHz, 1 target up to 10 MHz, 1 controller - target up to 12.9 MHz
- SPI interface:
- ST54L_CLF: 1 master up to 17 MHz, 1 master (up to 17 MHz) - slave (up to 26 MHz)
- ST54L_SE:
- 1 slave up to 26 MHz
- 1 master (up to 21 MHz) - slave (up to 26 MHz)
- I2C interface supporting standard, Fast, and Fast+ modes.
- SWP master interfaces up to 1.695 Mbit/s:
- 2 SWP UICC support
- 1 SWP external SE support
- ISO/IEC 7816-3 interface
- GPIOs
- Dedicated Chip Enable pins for the ST54L_SE/ST54L_CLF
- I3C interfaces:
- Secure microcontroller
- Arm® Cortex® M35P 32-bit RISC core
- 3.3 Mbytes of flash memory
- 4 Kbytes memory cache
- 100 Kbytes of user RAM
- Selectable ultralow power hibernate and standby states
- Supports state-of-the-art secure element operating systems
- CC EAL6+ certification
- Hardware security-enhanced DES & AES accelerators
- MIFARE Classic®1 cryptography hardware accelerator
- NESCRYPT coprocessor for public key cryptography algorithm
- Supports embedded-SIM (eSIM) applications in compliance with the GSMA specification
- Secure ranging support in connection with an external UWB sub-system
- Electrical characteristics
- Battery voltage support from 2.4 V to 5.1 V
- I/O dedicated voltage level (VPS_IO): 1.2 V and 1.8 V compatibility
- Supports Class B and C operating conditions for UICC – Class D ready
- Ambient operating temperature -30 to + 85 °C
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