X-CUBE-PERF-H7RS

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STM32H7Rx/7Sx performance software expansion for STM32Cube

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Description

Description

The X-CUBE-PERF-H7RS Expansion Package aims to demonstrate the performance of the STM32H7Rx/7Sx architecture with its Arm® Cortex®-M7 able to run at up to 600 MHz. The core instruction and data caches unleash its performance with zero-wait-state-like execution from different memories. The memories can be either internal or external. The core can access them through the TCM or AXIM buses, with or without encryption.

The Expansion Package is provided with two projects, each including several configurations for the STM32H7S78-DK Discovery kit:

  • The FFT project demonstrates the cycles needed for the calculation, in the frequency domain, of the maximum energy of a sine wave input signal. The demonstration uses complex FFT, complex magnitude, and maximum functions.
  • The bandwidth project demonstrates the STM32H7Rx/7Sx bandwidth performance for data transfer between internal memories or between internal and external memories.

An FFT use case (provided by the CMSIS library) is proposed as an example with two toolchains: Keil® (MDK-ARM) and IAR Systems® (EWARM).

Each configuration allows the execution of application code and data storage in different memory locations according to the chosen configuration.

When the instruction and data caches are enabled, the firmware results demonstrate that performance is similar when the code execution or data storage uses internal or external memories located in different domains. The results also highlight the impact of the MCE usage both on the cycles needed and bandwidth.

The bandwidth benchmark is proposed with three toolchains: Keil® (MDK-ARM), IAR Systems® (EWARM), and STMicroelectronics (STM32CubeIDE). The bandwidth is measured:

  • For read and write from and to the external PSRAM, either for sequential or nonsequential transfer according to the selected configuration
  • For read from the external flash memory, either for sequential or nonsequential transfer according to the selected configuration

An AXI-SRAM to AXI-SRAM transfer bandwidth is also measured.

For more details, refer to the "Introduction to STM32H7Rx/7Sx system architecture and performance" application note (AN6062).

  • All features

    • STM32H7Rx/7Sx performance demonstrator
    • Code execution and data storage in different memory locations
    • Bandwidth measurement for sequential and nonsequential transfer to and from external memories
    • Arm® Cortex®-M7 processor
    • Instruction cache (ICACHE)
    • Data cache (DCACHE)
    • Memory cipher engine (MCE) impact on execution and bandwidth
    • AXI and AHB bus matrices

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