STM32MP233F

Description

STM32MP23xC/F devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

STM32MP23xC/F devices also embed a Cortex®-M33 32-bit RISC core operating at up to 400 MHz frequency. The Cortex®-M33 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security.

STM32MP23xC/F devices can also embed a 3D graphic processing unit (VeriSilicon®, OpenGL ES 3.1, Vulkan 1.3, OpenCL 3.0, OpenVX 1.3) running at up to 400 MHz, with performances up to 66.5 Mtriangle/s, 400 Mpixel/s.

The graphic processing unit can provide a neural processor unit (VeriSilicon®, TensorFlowLite, ONNX, Linux NN) running at up to 400 MHz.

STM32MP23xC/F devices provide an external SDRAM interface supporting external memories up to 32‑Gbit density (4 Gbytes), 16-bit DDR3L up to 1066 MHz, 16-bit LPDDR4 or DDR4 up to 1200 MHz. The SDRAM content can be encrypted with AES-128.

The devices incorporate high-speed embedded memories: 776 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video SRAM (which can be used as general purpose), two banks of 128 Kbytes each of AHB SRAM, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multi-layer AXI interconnect supporting access to internal and external memories.

Each device offers three ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, 4 general-purpose 32‑bit timers, two PWM timers for motor control, five low-power timers, and a true random number generator (RNG), and cryptographic acceleration cells.

STM32MP23xC/F devices offer a video decoder.

The devices support 4 multi-function digital filters.

The devices feature the following standard and advanced communication interfaces.

Standard peripherals

• four I2Cs
• three I3Cs
• four USARTs and three UARTs
• one low-power UART
• six SPIs, three I2Ss full-duplex master/slave. The I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock.
• four SAI serial audio interfaces
• one SPDIF Rx interface
• three SDMMC interfaces
• an USB 2.0 Host with embedded Hi-Speed PHY
• an USB 2.0 dual-role data with Hi-Speed PHYs
• two FDCAN interfaces, including one supporting TTCAN mode (optional)
• two Gigabit Ethernet Interface, with TSN support (optional)

Advanced peripherals including

• a flexible memory control (FMC) interface
• two Octo-SPI flash memory interface, with on-the-fly content decryption
• two camera interfaces for CMOS sensors, one with basic ISP, demosaicing and parallel or MIPI CSI interface
• an LCD-TFT display interface
• a MIPI DSI display interface (optional)
• an LVDS display interface (optional)

A comprehensive set of power-saving mode allows the design of low-power applications.

STM32MP23xC/F devices are proposed in various packages up to 424 balls with 0.5 mm to 0.8 mm pitch. The set of included peripherals can change with the selected device.

These features make STM32MP23xC/F devices suitable for a wide range of consumer, industrial, white goods and medical applications.