STM32MP235D

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MPU with Dual Arm Cortex-A35 @ 1.5GHz, Cortex-M33 @ 400MHz, 2xEthernet, 2xFD-CAN, LVDS/DSI, H.264 dec, 3D GPU, AI/NN

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Overview

Product overview

Key Benefits

Key Benefits

Cost-effective on the edge solution

Optimized for cost and performance, dual Cortex-A35 and Cortex-M33, lower power consumption, extended temperature range.

Extensive ecosystem

OpenSTLinux ecosystem, Yocto and Buildroot support, and minimum 5-year maintenance industrial-grade longevity.

Processing and edge AI capabilities

Up to dual Cortex-A35, Cortex-M33, neural processing unit (NPU) with 0.6 TOPS and graphics processing unit (GPU).

Description

STM32MP23xA/D devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

STM32MP23xA/D devices also embed a Cortex®-M33 32-bit RISC core operating at up to 400 MHz frequency. The Cortex®-M33 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security.

STM32MP23xA/D devices can also embed a 3D graphic processing unit (VeriSilicon®, OpenGL ES 3.1, Vulkan 1.3, OpenCL 3.0, OpenVX 1.3) running at up to 400 MHz, with performances up to 66.5 Mtriangle/s, 400 Mpixel/s.

The graphic processing unit can provide a neural processor unit (VeriSilicon®, TensorFlowLite, ONNX, Linux NN) running at up to 400 MHz.

STM32MP23xA/D devices provide an external SDRAM interface supporting external memories up to 32‑Gbit density (4 Gbytes), 16-bit DDR3L up to 1066 MHz, 16-bit LPDDR4 or DDR4 up to 1200 MHz.

The devices incorporate high-speed embedded memories: 776 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video SRAM (which can be used as general purpose), two banks of 128 Kbytes each of AHB SRAM, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multi-layer AXI interconnect supporting access to internal and external memories.

Each device offers three ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, 4 general-purpose 32‑bit timers, two PWM timers for motor control, five low-power timers, and a true random number generator (RNG).

STM32MP23xA/D devices offer a video decoder.

The devices support 4 multi-function digital filters.

The devices feature the following standard and advanced communication interfaces.

Standard peripherals

  • four I2Cs
  • three I3Cs
  • four USARTs and three UARTs
  • one low-power UART
  • six SPIs, three I2Ss full-duplex master/slave. The I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock.
  • four SAI serial audio interfaces
  • one SPDIF Rx interface
  • three SDMMC interfaces
  • an USB 2.0 Host with embedded Hi-Speed PHY
  • an USB 2.0 dual-role data with Hi-Speed PHYs
  • two FDCAN interfaces, including one supporting TTCAN mode (optional)
  • two Gigabit Ethernet Interface, with TSN support (optional)

Advanced peripherals including

  • a flexible memory control (FMC) interface
  • two Octo-SPI flash memory interface
  • two camera interfaces for CMOS sensors, one with basic ISP, demosaicing and parallel or MIPI CSI interface
  • an LCD-TFT display interface
  • a MIPI DSI display interface (optional)
  • an LVDS display interface (optional)

A comprehensive set of power-saving mode allows the design of low-power applications.

STM32MP23xA/D devices are proposed in various packages up to 424 balls with 0.5 mm to 0.8 mm pitch. The set of included peripherals can change with the selected device.

These features make STM32MP23xA/D devices suitable for a wide range of consumer, industrial, white goods and medical applications.

  • All features

    • Includes ST state-of-the-art patented technology.
    • Cores
      • Up to 64-bit dual-core Arm® Cortex®-A35
        • Up to 1.5 GHz
        • 32-Kbyte I + 32-Kbyte D level 1 cache for each core
        • 512-Kbyte unified level 2 cache
        • Arm® NEON™ and Arm® TrustZone®
      • 32-bit Arm® Cortex®-M33 with FPU/MPU
        • Up to 400 MHz
        • L1 16-Kbyte I / 16-Kbyte D
        • Arm® TrustZone®
    • Memories
      • External DDR memory up to 4 Gbytes
        • Up to DDR3L-2133 16-bit
        • Up to DDR4-2400 16-bit
        • Up to LPDDR4-2400 16-bit
      • 776-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain
      • Two Octo-SPI memory interfaces
      • Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC
    • Security/safety
      • TrustZone® peripherals, active tamper, environmental monitors, display secure layers, hardware accelerators
      • Complete resource isolation framework
    • Reset and power management
      • 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply
      • POR, PDR, PVD, and BOR
      • On-chip LDO and power-switches for RETRAM, BKPSRAM, VSW, and SmartRun domains
      • Dedicated supplies for Cortex®-A35 and GPU/NPU (if present)
      • Internal temperature sensors
      • Low-power modes: Sleep, Stop, and Standby
      • DDR memory retention in Standby mode
      • Controls for PMIC companion chip
    • Low-power consumption
    • Clock management
      • Internal oscillators: 64 MHz HSI, 4/16 MHz MSI, 32 kHz LSI
      • External oscillators: 16-48 MHz HSE, 32.768 kHz LSE
      • Up to 8× PLLs with fractional mode
    • General-purpose inputs/outputs
      • Up to 144 secure I/O ports with interrupt capability
        • Up to 6 wake-up inputs
        • Up to 7 tamper input pins + 5 active tampers output pins
    • Interconnect matrix
      • Bus matrices
        • 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz
        • 32-bit Arm® AMBA® AHB interconnect, up to 400 MHz
    • 3 DMA controllers to unload the CPU
      • 48 physical channels in total
      • 3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16 channels each
    • Up to 39 communication peripherals
      • 4× I2C FM+ (1 Mbit/s, SMBus/PMBus®)
      • 3× I3C (12.5 Mbit/s)
      • 3× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART
      • 6× SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock)(+2 with OCTOSPI + 4 with USART)
      • 4× SAI (stereo audio: I2S, PDM, SPDIF Tx)
      • SPDIF Rx with 4 inputs
      • 3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)
      • Up to 2× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN)
      • 1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY
      • 1× USB 2.0 high-speed dual role data with embedded 480 Mbits/s PHY
      • 1× USB Type-C® Power Delivery control with two CC lines PHY
      • Up to 2× Gigabit Ethernet interfaces
        • 1× Gigabit Ethernet GMAC with one external PHY interface (optional)
        • 1× Gigabit Ethernet GMAC with one external PHY interface
        • TSN, IEEE 1588v2 hardware, MII/RMII/RGMII
      • Camera interface #1 (5 Mpixels at 30 fps)
        • MIPI CSI-2®, 2× data lanes up to 2.5 Gbit/s each
        • 8- to 16-bit parallel, up to 120 MHz
        • RGB, YUV, JPG, RawBayer with Lite-ISP
        • Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines
      • Camera interface #2 (1 Mpixels at 15 fps)
        • 8- to 14-bit parallel, up to 80 MHz
        • RGB, YUV, JPG
        • Cropping
      • Digital parallel interface up to 16-bit input or output
    • 6 analog peripherals
      • 3 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)
      • Internal temperature sensor (DTS)
      • 1× multifunction digital filter (MDF) with up to 4 channels/4 filters
      • Internal (VREFBUF) or external ADC reference VREF+
    • Graphics
      • Optional 3D GPU: VeriSilicon® - Up to 400 MHz
        • OpenGL® ES 3.1 - Vulkan 1.3
        • OpenCL™ 3.0, OpenVX™ 1.3
        • Up to 66.5 Mtriangle/s, 400 Mpixel/s
      • LCD-TFT controller, up to 24-bit // RGB888
        • Up to FHD (1920 × 1080) at 60 fps
        • 3 layers including a secure layer
        • YUV support, 90° output rotation
      • Optional MIPI DSI®, 4× data lanes, up to 2.5 Gbit/s each
        • Up to QXGA (2048 × 1536) at 60 fps
      • Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), 4× data lanes, up to 1.1 Gbit/s per lane
        • Up to FHD (1920 × 1080) at 60 fps
    • Artificial intelligence
      • Optional NPU: VeriSilicon® - Up to 400 MHz
        • TensorFlowLite - ONNX - Linux NN
    • Video processing
      • Optional hardware video decoder up to 600 MHz
        • H264/VP8 up to FHD (1920×1080) at 60 fps
        • JPEG up to 500 Mpixel/s
        • 128 Kbytes of video RAM
    • Up to 32 timers and 5 watchdogs
      • 4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
      • 2× 16-bit advanced motor control timers
      • 10× 16-bit general-purpose timers (including 2 basic timers without PWM)
      • 5× 16-bit low-power timers
      • Secure RTC with subsecond accuracy and hardware calendar
      • Up to 2× 4 Cortex®-A35 system timers (secure, non-secure, virtual, hypervisor)
      • 2× SysTick Cortex®-M33 timer (secure, non-secure)
      • 5× watchdogs (4× independent and 1× window)
    • Hardware acceleration
      • ECDSA verification with SCA
      • HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC
      • True random number generator
      • CRC calculation unit
    • Debug mode
      • Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
    • 12288-bit fuses including 96-bit unique ID
    • All packages are ECOPACK2 compliant

Circuit Diagram

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The current status of a product:
Active: Product is in volume production
Evaluation: Product is under characterization. Limited Engineering samples available
Preview: Product is in design stage
Target: Product is in design feasibility stage.No commitment taken to produce
Proposal: Marketing proposal for customer feedback.No commitment taken to design or produce
NRND: Not Recommended for New Design.Product is in volume production only to support customers ongoing production.Marketing description of the package type.Compliancy of the device with industry requirement domains (IRD)The RoHS status of a product:
ECOPACK 1: Initial grade to identify European RoHS compliant products.
ECOPACK 2: New grade to identify brominated chlorinated and antimony oxide flame retardant free products.
ECOPACK 3: Halogen free RoHS exemptions free products.
(*): ECOPACK 2 version available upon request.
(**): Some versions still existing in ECOPACK 1 or not compliant.Longevity Commitment in yearsLongevity Starting DateThe current status of a product:
Active: Product is in volume production
Evaluation: Product is under characterization. Limited Engineering samples available
Preview: Product is in design stage
Target: Product is in design feasibility stage.No commitment taken to produce
Proposal: Marketing proposal for customer feedback.No commitment taken to design or produce
NRND: Not Recommended for New Design.Product is in volume production only to support customers ongoing production.Budgetary PriceMarketing description of the package type.Storage method used to contain product.Main country of assembly or fabrication of the product.ECCNs are five character alpha-numeric designations used on the Commerce Control List to identify dual-use items for export control purposes. ECCNs are five character alpha-numeric designations used on the Commerce Control List to identify dual-use items for export control purposes.The value as specified by level (minTypMax) of the ambient temperature (in Cel) in which this item was designed to operate.The value as specified by level (minTypMax) of the ambient temperature (in Cel) in which this item was designed to operate.