STM32WBA62PI

Description

The STM32WBA6xxx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth^® LE and with IEEE 802.15.4-2015. They contain a high-performance Arm^® Cortex^®-M33 32-bit RISC core, and operate at a frequency of up to 100 MHz.

The devices integrate a 2.4 GHz RADIO supporting Bluetooth^® LE, Matter, Thread, and Zigbee^®, and make possible to use proprietary protocols and concurrent operation modes. They provide support for an array of up to eight antennas, and an external power amplifier. PTA (packet traffic arbitration) interface is supported as well.

The Cortex-M33 core features a single-precision floating-point unit (FPU), supporting all the Arm single-precision data-processing instructions and all the data types. This core implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (up to 2-Mbyte flash, up to 512-Kbyte SRAM), an extensive range of enhanced I/Os, and peripherals connected to AHB and APB buses on the 32-bit multi-AHB bus matrix.

The security foundation is compliant with the TBSA (trusted-based security architecture) requirements from Arm. It embeds the features needed to implement secure boot, secure data storage, and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels readout protection and debug unlock with password.

Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories.

The devices feature protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure, and hide protection areas.

Dedicated peripherals reinforce security: a fast AES coprocessor, a secure AES coprocessor with DPA resistance and hardware unique key that can be shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance, a HASH hardware accelerator, and a true random number generator.

The devices offer active tamper detection and protection against transient perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications.

Hardware semaphores allow synchronization between software processes.

The devices offer one 12-bit ADC (2.5 Msps), up to two comparators, a low-power RTC, up to two 32-bit general-purpose timer, one 16-bit PWM timer for motor control, three 16-bit general-purpose timers, and two 16-bit low-power timers. They also feature standard and advanced communication interfaces, namely up to four I2Cs, up to three SPIs, one SAI, up to three USARTs, one low-power UART, and one USB OTG high-speed.

The devices operate in the -40 to 85 °C (105 °C junction) and -40 to 105 °C (125 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.

The design of low-power applications is enabled by a comprehensive set of power-saving modes.

Many peripherals (including radio, communication, analog, and timer peripherals) can be functional and autonomous in Stop mode with direct memory access thanks to background autonomous mode (BAM) support.

Some independent power supplies are supported, like an analog independent supply input for ADC and comparators, USB OTG high-speed, 14 GPIOs and dedicated supply inputs for the 2.4 GHz RADIO.

The devices offer four packages, from 48 to 121 pins, with or without SMPS.