ESDプロテクション

ESD stands for electrostatic discharge. ESD is defined by the ESD association as the rapid, spontaneous transfer of electrostatic charge induced by a high electrostatic field.

It is the result of static electricity discharge. Static electricity is the collection of electrically charged particles on the surface of a material.

Various materials have a tendency of either:

• Giving up electrons and gaining positive (+) charges
• Attracting electrons and gaining negative (-) charges

Electrostatic discharge will cause potential failure on the integrated circuits of your PCB.

These failures are called electrical over stress (EOS), resulting in silicon melting, oxide punch-through, junction damage, metallization damage or degradation affecting the long-term reliability of your electronic system.

A survey from the EOS industry council shows that 30% of customer claims are due to ESD or EOS (electrical over stress). Furthermore, the miniaturization of the components is increasing the integrated circuits sensitivity to ESD.

Eye diagram information is defined by standards like USB, HDMI etc.

The ESD protection device compliancy with eye diagram is specified in the related datasheet, for example in HSP051-4M10.

Eye diagrams can be negatively impacted by wrong ESD protection selection. An extremely high capacitance ESD protection may cause the eye diagram test to fail.

On the other hand requirements like attach / detach requirements (more functional) cannot be impacted by the ESD protection because ESD protection is transparent (high impedance and low capacitance in parallel with datalines) in normal operation.

TD 4.1.2 is related to USB Type-C test for Rp that must not be present for source application when source is OFF. ESD protection will be transparent in this test.

TD 4.12.2 is related to USB Type-C test checking if there is only one upstream port in a hub port device.

The absolute maximum rating (AMR) voltage value is not relevant because it is a DC measured voltage and not measured for a transient voltage, hence an intrinsically pessimistic value (AMR value is too low).

In the presented example the AMR value is too low, AMR = 5.5 V while the ESD destruction value is 12 V. The best approach to select the V_CL is to apply the SEED methodology described in our ESD Webinar.

If any TLP information is available for the IC to be protected, the lower V_CL will ensure the better protection.

14 dBm corresponds to 1.6 V max on 50 Ω load. As a consequence, ESDARF02-1BU2CK matches the requirement at 868 MHz (no RF losses, V_MAX < V_RM and bi-directionnal for RF signaling).

Power lines require high current capability surge protection because lightning and switching transients are present on these lines (cf IEC61000-4-5) as well as some functional events generating inrush currents (full-load unplugged, adapter failure, etc). STMicroelectronics protection devices against IEC61000-4-5 surges are available.

ESDA15P60-1U1M fits 12 V DC outputs protection for both ESD (IEC61000-4-2) and switching transients (cf IEC61000-4-5).

The original question during the webinar was: My design is analogic measurement current in an isolated high tension (25 kV) system. Sometimes, we have breakdowns, and we have damage (aop 1st stage AD4610 or a voltage regulator (+5 V or -15 V or +15 V). I tried to insert protective components without performance loss. I measured 5 nA current and some TVS diodes have leakage current 1 or 10 or 100 nA. Any useful reference in future can be test, it might be differential measurement.

For that specific case, 2 ESD protections on common mode may be better than a single ESD protection in differential. We recommend ESDZV5H-1BU2 for +/-5 V and ESDLC20-1BF4 for +/-20 V.

Check the ESD specification for your RS-485 transceiver: if it is only rated per HBM, then system-level ESD is needed (IEC61000-4-2). To protect RS485 transceiver, ESDA14V2BP6 is recommended.

Please check schematic in figure ESD14V2BP6 protection device schematic in AN5245.

ST485 transceiver can be split in 2 families:

• with system ESD protection (ST485E series)
• without system ESD protection (ST485 series)

When ST485E series cannot be placed close to the ESD source, it is required to use external ESD protections in order to avoid any EMI coupling with internal PCB tracks. EMI coupling induced by ESD can generate latch-up failures in your system.

Yes, this specific product requires an external ESD protection. For 1 Mbps signal with 5.5 V AMR, we recommend USBLC6-2SC6 or USBLC6-4SC6 according to the number of lines to be protected.

Yes, it is a simplified but functional schematic. Real schematic is more complex with serial inductors.

The track maximum DC current is not critical due to the ESD event duration (≈100 ns).

You can find ST PSpice ESD protection models under SPICE models.

We usually connect it to the GND of the system.

ESD protection ground must be connected to the reference GND plane of the protected I/O to limit or avoid any parasitic inductance effect due to multiple ground planes connection.

The current is flowing to the ground.

It is only necessary to protect GPIO exposed to system-level ESD (connector, button) otherwise embedded HBM is enough.

ESD cannot be assimilated to simple conduction thought a metal track, it is a charge equilibrium between 2 systems. As a consequence, airdischarge can appear and non-conductive materials can let the charge flow (e.g. side key buttons on smartphone need to be protected).

Other types of ESD protection can be: MOV, polymer and PCB spark gap. All of them present very high clamping voltage and reliability issues that are not compatible with ESD protection of sensitive ICs.

Adding a serial resistor can be recommended because it will decrease the clamping voltage on protected IC I/O. But for some interfaces, adding a serial resistor may exceed the line impedance specified in the standard or decrease the bandwidth.

TVS protects against transient over-voltage while Zener is for voltage regulation, because not rated against surges nor over-voltages. To protect against DC over-voltage, an over-voltage protection (OVP) is required. OVP and TVS can be used together with TVS maximum clamping voltage slightly below OVP AMR.

Secure margin between AMR and maximum ESD clamping voltage before destruction can be very scattered. To select the best ESD protection, bandwidth must not be over-sized, V_RM must be just slightly higher than line voltage in order to lower the clamping voltage.

On power line, capacitor are selected to fit power requirement. The capacitor rated voltage must be higher than the clamping voltage of the TVS to avoid capacitor degradation or destruction when surge event occurs.

Power inputs are usually protected using TVS rather than ESD protection components.

Automotive TVS portfolio is available here.

Industrial TVS portfolio is available here.

Standard ESD protection (ESD051-1BF4) can be used for LED protection. Bidirectional protection is recommended to test LED mounted on reverse.

We use Teseq ESD gun. We do not have any ESD gun benchmark.

In an ESD-controlled environment, a conductive lab coat with ESD wrist connected to the ground are recommended.

EMITECH is a French Lab.

During soldering (connector as example), only HBM is relevant but the environment must be under control (operator with wrist connected to ground, solder iron connected to ground).

PINs that do not go outside the PCB do not require specific ESD protection but special care is mandatory for handling (conductive lab coat with ESD wrist connected to the ground).

Feel free to reach us via our local support.

We use a high bandwidth, high sample rate oscilloscope on 50Ω with 40dB external input attenuation. See STMicroelectronics AN3353.

A Zener diode is used for voltage regulation under DC-current condition but neither their silicon nor their package is rated for transient surge dissipation.

Only ESD or transient voltage suppressor (TVS) specify the transient surge they can dissipate.

The best parameter to qualify the efficiency of an ESD protection is the clamping voltage because if your 30 kV ESD diode has a poor clamping voltage it means your application will be more sensitive to transient voltages.

ESD robustness higher than 8 kV has to be taken into account only if your application requires it like in automotive standard ISO10605.

Because TLP data are not specified by ICs suppliers, you can only rely on the V_RM of the line to be protected to select your ESD protection. In this case the clamping voltage after an 8 kV ESD contact discharge can help you to compare ESD protection efficiency.

Yes, but keep in mind that each interface has its own requirement. For example you may choose a low capacitance ESD in a 2-line package to protect D_plus and D_minus pins of an USB connector in order to keep the best signal integrity on these datalines whereas you may choose a single line ESD protection with high capacitance for a touch button to lower signal bouncing.

No, ESD protection according to CDM is granted for all ICs because it is related to component level protection like HBM.

V_RM is the maximal operating voltage of the protection to ensure a good transparency of the application voltage signal in the normal operation. The V_RM of the ESD protection must be higher than the normal signal voltage amplitude. If the signal is negative and positive, the protection must be bi-directional to avoid rectifier phenomenon. If the signal to be protected is only positive, an unidirectional protection is preferred. Along with the V_RM voltage there is also the protection current leakage parameter called I_RM. A too high leakage current can affect the system overall consumption but it can also change a data line voltage. Usually, the leakage current is below 1 μA at V_RM (ESDZV5 has I_RM e.g. at 100 nA maximum).

Standard ESD protections activate at breakdown voltage (called V_BR) and their voltage increases with the current linearly to clamping voltage. The snap-back protection instead has a snap-back effect which means that it lowers its clamping voltage after the protection is triggered. The holding voltage (V_H) is the lowest voltage when the snap-back protection has turnedon. The lower is the holding voltage, the better is the clamping voltage.

The figures below show on the left the I/V characteristics of a standard ESD protection and on the right the I/V characteristics of a snapback ESD protection.

The resistor is always part of a system which has some specific characteristic. E.g. Operating voltage. In order to protect the system, your have to place a system level ESD protection with appropriate voltage linked to V_RM on the weak point from where the ESD impact can come. This way you will also protect your resistor which have typical nominal voltage from 25 V to 100 V;

In ST we are focusing on factory automation applications in general and so also on sensors specifically. For example we have specific ICs to support the IO-Link sensor communication on the sensor slave side as well as on the IO-Link master side.

To protect 3 wire proximity sensors we propose a protection device called SPT01-335 which can protect 24 V proximity sensors. It implements the reverse polarity and the overvoltage protection of the sensor power supply and also this device integrates the power switch overvoltage protection in a small QFN 3x3 mms in size.

No, ESD protection according to CDM is granted for all IC because it is related to component level protection like HBM.