製品概要
概要
Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected updatable automated and electrified cars. They have superior real-time and safe performance (with highest ASIL-D capability). Bringing hardware-based virtualization technology to MCUs, they ease the development and integration of multiple source software onto the same hardware while maximizing the resulting software performance. They offer high-efficiency OTA reprogramming capability with fast new image download and activation at almost no memory overhead thanks to SR6 unique built-in dual-image storage tailored to OTA reprogramming needs. They also provide high-speed security cryptographic services, for instance for network authentication.
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特徴
- AEC-Q100
- SR6 integration MCUs:
- Have superior real-time and safe performance (with highest ASIL-D capability)
- Bring hardware-based virtualization technology to MCUs for simplified multiple software integrations at optimized performance
- Have built-in fast and cost-effective OTA reprogramming capability (with built-in dual-image storage)
- Offer high-speed security cryptographic services, for example for network authentication
- Cores and accelerators
- 4 × 32-bit Cortex®‑R52+ cores (2 of them with checker cores, and 2 in split-lock configuration):
- Configurable as either 4 cores (2 of them in lockstep configuration) or 3 cores (all of them in lockstep configuration)
- Arm® v8-R compliant
- Single precision floating-point unit (FPU)
- New privilege level for real-time virtualization
- 1 core with Neon™ extensions (for example SIMD, dual precision FPU)
- 2 Cortex®‑M4 multipurpose accelerators, both in lockstep configuration
- 4 eDMA engines in lockstep configuration
- Ethernet switch:
- 2 external gigabit (GB) ports with line-rate MACsec
- 6 data + 1 host internal virtualized ports
- Time-sensitive networking
- Audio-video transport protocol (AVTP)
- Media clock recovery/generation
- L2 forwarding, L2+ routing
- ASIL-B target
- 4 × 32-bit Cortex®‑R52+ cores (2 of them with checker cores, and 2 in split-lock configuration):
- メモリ
- Up to 16 MB on-chip nonvolatile memory (NVM):
- PCM (phase-change memory) as nonvolatile memory
- 15 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2× 15 MB
- 1024 KB HSM-dedicated code NVM
- 384 KB data NVM (256 KB + 128 KB dedicated to HSM)
- Up to 3840 KB on-chip general-purpose SRAM
- Up to 16 MB on-chip nonvolatile memory (NVM):
- Security: 2nd generation hardware security module
- Cybersecurity: ISO/SAE 21434 compliance (refer to the cybersecurity reference manual for details)
- On-chip high-performance security module with full support for e-safety vehicle intrusion protected applications (EVITA)
- Symmetric and asymmetric cryptography processor
- High-performance lock-stepped AES-light security subsystem for fast ASIL-D cryptographic services
- Two MACsec accelerators integrated on each Ethernet link
- Safety: comprehensive new-generation ASIL-D safety concept
- New state-of-the-art safety measures at all levels of the architecture for most efficient implementation of ISO 26262 ASIL-D functionalities
- Complete hardware virtualization architecture built on Cortex®‑R52+ new privilege mode (best-in-class software isolation, real-time support for multiple virtual machines/applications)
- Device standby/low-power modes
- Versatile low-power modes
- Ultra-low power: standby mode for lowest quiescent current with optimized active subsystem (for example standby RAM) and wake-up capability
- Smart low-power: smart power mode with Cortex®‑M4 subsystem, extended communications interfaces, and ADC peripheral
- Peripheral, I/O, and communication interfaces
- 24 LINFlexD modules
- 1 dual-channel FlexRay controller
- 10 queued serial peripheral interface (SPIQ) modules
- 2 DSPI with shifted PWM serialization support for lighting applications
- 6 I²C interfaces
- Enhanced audio support that enables audio over Ethernet:
- Ethernet controller with AVB support
- Medial clock recovery with integrated audio PLL
- Two integrated interchip sound (I²S)/time-division multiplexed (TDM) interfaces
- Integrated sample rate converters (6 channels on each I²S interface)
- 2 SENT modules (4 channels each)
- 2 PSI5 modules (2 channels each)
- 1 peripheral component interconnect express (PCIe) Gen2 controller
- Gen2 PHY: Gen1 (2.5 GT/s), Gen2 (5.0 GT/s)
- Gen3 MAC
- Two lanes
- Configurable controller with one or two lanes
- Enhanced analog-to-digital converter system with:
- 4 separate 12-bit SAR analog converters (including one supervisor/safety ADC).
- One 9-bit SAR analog converter for device standby/low-power mode
- Advanced timed I/O capability:
- Generic timer module (GTM4184)
- Communication interfaces:
- Two 10/100/1000 Mbit/s Ethernet controllers compliant with IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN, and EMC optimized SGMII
- Two 10 Mbit/s Ethernet controllers compliant with 10BASE-T1S and the OPEN Alliance 3-pin (OA3p) interface
- 15 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M_TTCAN), all supporting flexible data rate (ISO CAN FD®)
- 2 CAN XL® interfaces
- External memory interfaces
- 2 octo-SPI IPs to support HyperBus™ memory (flash/RAM) devices
- 1 SDMMC interface
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STMicroelectronics - SR6G6C6
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品質 & 信頼性
| 製品型番 | マーケティング･ステータス | パッケージ | グレード | RoHSコンプライアンスグレード | 材料宣誓書** |
|---|---|---|---|---|---|
| SR6G6C6A0xx | 計画中 | FPBGA 476 21.3X21.3X1.8 | インダストリアル | - | |
SR6G6C6A0xx
Package:
FPBGA 476 21.3X21.3X1.8Material Declaration**:
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サンプル & 購入
| 製品型番 | 製品ステータス | Budgetary Price (US$)*/Qty | STから購入 | Order from distributors | パッケージ | 梱包タイプ | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | CPU Clock Frequency (MHz) (max) | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| SR6G6C6A0xx | | | distributors 販売代理店に在庫がない場合は、STのセールス･オフィスまでお問い合わせください |
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SR6G6C6A0xx 計画中
販売代理店に在庫がない場合は、STのセールス･オフィスまでお問い合わせください
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