製品概要
概要
The EVSTGAP2SICSAC is a half bridge evaluation board designed to evaluate the STGAP2SICSAC isolated single gate driver
The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making the device also suitable for mid and high power inverter applications such as motor drivers in industrial applications equipped with SiC MOSFET power switches.
The device has a single output pin and Miller CLAMP function that prevents gate spikes during fast commutations in half-bridge topologies. This configuration provides high flexibility and bill of material reduction for external components.
The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to easily design high reliability systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction.
The device allows implementing negative gate driving, and the on board isolated DC-DC converters allows working with optimized driving voltage for SiC MOSFET.
The EVSTGAP2SICSAC board allows evaluating all the STGAP2SICSAC features while driving a half-bridge power stage with voltage rating up to 520 V. It is possible to increase bus voltage by replacing the power switches with appropriate devices in H2PACK-7L or H2PACK-2L or HU3PAK package and the C29 capacitance if needed.
The board components are easy to access and modify in order to make driver performance evaluation easier under different application conditions and fine adjustment of final application components.
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特徴
- Board
- Half bridge configuration, high voltage rail up to 520 V
- SCT055H65G3AG: 650 V, 58 mΩ typ., 30 A 3rd generation SiC MOSFET
- Negative gate driving
- On-board isolated DC-DC converters to supply high-side and low-side gate drivers, fed by VAUX = 5 V, with 5.2 kV maximum isolation
- VDD logic supplied by on-board generated 3.3 V or VAUX = 5 V
- Easy jumper selection of driving voltage configuration: +17/0 V; +17/-3 V; +19/0 V; +19/-3 V
- デバイス
- AEC-Q100 qualified
- High voltage rail up to 1200 V
- Driver current capability: 4 A source/sink @ 25 °C
- 4 A Miller CLAMP
- Overall input-output propagation delay: 45 ns
- UVLO function
- Gate driving voltage up to 26 V
- 3.3 V, 5 V TTL/CMOS inputs with hysteresis
- Temperature shut down protection
- 6 kV Galvanic isolation
- UL 1577 recognized
- Board
