SPC570S40E1

概要

はじめる

Partner products

セールスブリーフケース

Please enter your desired search query and search again

製品概要

概要

The SPC570Sx is a family of next generation microcontrollers built on the Power Architecture embedded category.

The SPC570Sx family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of Chassis and Safety electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 80 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.

特徴
AEC-Q100 qualified

High performance e200z0h dual core

32-bit Power Architecture technology CPU

Core frequency as high as 80 MHz

Single issue 4-stage pipeline in-order execution core

Variable Length Encoding (VLE)

Up to 544 KB (512 KB code + 32 KB data, suitable for EEPROM emulation) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation

Up to 48 KB on-chip general-purpose SRAM

Multi-channel direct memory access controller (eDMA paired in lockstep) with 16 channels

Comprehensive new generation ASILD safety concept

Safety of bus masters (core+INTC, DMA) by delayed lockstep approach

Safety of storage (Flash, SRAM) by mainly ECC

Safety of the data path to storage and periphery by mainly End-to-End EDC (E2E EDC)

Clock and power, generation and distribution, supervised by dedicated monitors

Fault Collection and Control Unit (FCCU) for collection and reaction to failure notifications

Memory Error Management Unit (MEMU) for collection and reporting of error events in memories

Boot time MBIST and LBIST for latent faults

Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms

Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST

Further measures on dedicated peripherals (e.g. ADC supervisor)

Junction temperature sensor

8-region system memory protection unit (SMPU) with process ID support (tasks isolation)

Enhanced SW watchdog

Cyclic redundancy check (CRC) unit

Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell
Nexus Class 3 debug and trace interface

Communication interfaces

2 LINFlexD modules, 3 deserial serial peripheral interface (DSPI) modules, and Up to 2 FlexCAN interfaces with 32 message buffers each

On-chip CAN/UART Bootstrap loader with Boot Assisted Flash (BAF). Physical Interface (PHY) can be

UART and CAN

2 enhanced 12-bit SAR analog converters

1.5 μs conversion time (12 MHz)

16 physical channels (fully shared between the 2 SARADC units)

Supervisor ADC concept

Programmable Cross Triggering Unit (CTU)

Single 3.3 V or 5 V voltage supply

4 general purpose eTimer units (6 channels each)

Junction temperature range -40 °C to 150 °C (165 °C grade optional)
続きを読む一部を表示